Felipe Rojas Barrantes

Microelectronics and Chip Design Specialist | Security IP Verification Engineer

München, DE.

About

Highly skilled Microelectronics and Chip Design professional currently pursuing an MSc. at Technische Universität München, bringing a strong background in VLSI design and high-speed link analysis. With extensive experience at Intel in Security IP verification and DDR memory interface validation for Xeon CPUs, I excel at leading complex verification efforts, optimizing test coverage, and driving innovation in hardware-based security features. My expertise spans sophisticated debug capabilities, automated test development, and advanced simulation techniques, positioning me to deliver significant impact in cutting-edge semiconductor development.

Work

Intel Corporation

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Security IP Verification Engineer

Costa Rica, Costa Rica

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Summary

Led advanced verification efforts for critical security IPs, ensuring data integrity and confidentiality in desktop/laptop CPUs through comprehensive test plan development and execution.

Highlights

Led Register Attribute and DFx verification for Protected Sideband IP (pSB), achieving a 100% test passing rate prior to project milestones, ensuring robust hardware-based security features.

Served as verification owner for Intel's foundational security IPs (USBr, CLink IP), ensuring the healthy security manageability engine (CSME) of client CPUs.

Managed the execution of verification tasks using advanced simulation techniques to maximize test coverage and identify critical corner cases within complex digital designs.

Performed and evaluated weekly regression runs using Netbatch Flow Manager, efficiently running multiple regressions from a single job feeder to ensure thorough IP design coverage.

Integrated testbench environments with IDE tools like DVT and GitHub Copilot AI, accelerating code development, debugging, and improving productivity by enhancing code navigation and simplifying legacy code maintenance.

Systematically analyzed waveforms, log files, and simulation outputs on multiple random seeds to isolate and detect problems within the design or verification environment.

Intel Corporation

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Research and Development Engineer

Costa Rica, Costa Rica

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Summary

Contributed to a research and development team focused on characterizing industry-standard protocols and analyzing high-speed complex circuits.

Highlights

Contributed to a research and development team responsible for characterizing industry-standard protocols, including DDR5, PCIe, and HBM3.

Studied the behavior of high-speed complex circuits, such as LJPLL, ADC, DAC, MC, and LDO, to inform design improvements.

Conducted studies on silicon degradation behavior over time, providing critical data for long-term product reliability and performance.

Intel Corporation

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Design Validation Engineer

Costa Rica, Costa Rica

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Summary

Validated DDR memory interfaces for Intel Xeon CPUs, developing Python-based test scripts and actively participating in critical analysis and debugging task forces.

Highlights

Collaborated on DDR memory interface validation for Intel Xeon CPUs (Post-Silicon), successfully enabling a Test Vehicle to validate DDR5 IP interface.

Developed a suite of Python-based test scripts utilizing VISA libraries for instrumentation control and automatization, characterizing circuits such as Xover and TX EQ.

Actively participated in task forces, demonstrating critical analysis and debugging skills alongside principal engineers to resolve complex issues.

Proposed an automated routing topology for DDR 5 signal driving and characterized pad capacitance for Xeon Server CPU, optimizing performance.

Proposed a methodology for Validation of DV Characterization of Memory Interfaces, enhancing validation processes and efficiency.

Conlith S.A

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IT Assistant Internship

Costa Rica, Costa Rica

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Summary

Provided essential IT support, managed hardware maintenance, and scheduled software updates, gaining foundational knowledge in integrated circuits.

Highlights

Provided comprehensive support to the IT department, ensuring smooth operational flow and timely issue resolution.

Managed the maintenance of computer hardware and scheduled software updates, contributing to system stability and performance.

Gained practical knowledge of integrated circuits used in printing machines, enhancing understanding of electronic components.

Education

Technische Universität München (TUM)

München, Germany, Germany
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MSc. Microelectronics and Chip Design

Universidad de Costa Rica

San Jose, Costa Rica, Costa Rica
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Academic Training Very Large Scale Integration (VLSI)

Instituto Tecnologico de Costa Rica

Cartago, Costa Rica, Costa Rica
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Bachelor's Degree Electronics Engineering

Publications

A new Methodology for Validation of Testbenches for DV Characterization of Memory Interfaces

Intel's DTTC (Design and Test Technology Conference)

Published a white paper detailing a novel methodology for validating testbenches used in Design Verification characterization of memory interfaces, contributing to industry best practices.

Languages

Spanish

English

Skills

Professional Skills

Critical Thinking, Prioritization, Time Management, Self Motivation, Customer Service.

Programming Languages

C, C++, Python.

Chip Design & Verification

Chip Design, Circuit Designs, Logic Design, VLSI, VLSI Designing, IP Verification, Formal Verification, IP Development, UVM, Universal Verification Methodology, RTL Coding, VHDL, System Verilog, Verilog.

Tools & Technologies

Synopsys Design Compilers, Synopsys VCS, Verdi, Cadence JasperGold, Git, DVT, GitHub Copilot, Microsoft Office, Linux, Windows, Oscilloscope, JBERT, VNA, VISA libraries.

Technical Expertise

Signal Integrity, High-Speed Links, High-level architecture specifications, Intel IPs (IOSF, USBr, CLink IP), DDR5, PCIe, HBM3, LJPLL, ADC, DAC, MC, LDO.

Projects

Final Graduation Project Development of a Methodology for Routing High-Frequency Analog Lines on a Processor Test Platform

Summary

Developed a methodology for routing high-frequency analog lines on a processor test platform, addressing critical challenges in signal integrity and performance for advanced circuit designs.